Semiconductor package and fabrication method thereof

ABSTRACT

A semiconductor package is provided, which includes: a packaging substrate having opposite first and second surfaces and a plurality of first and second conductive pads formed on the first surface; a chip having opposite active and inactive surfaces and disposed on the first conductive pads via the active surface thereof; a plurality of conductive posts formed on the second conductive pads, respectively; and a first encapsulant formed on the first surface of the packaging substrate for encapsulating the chip and the conductive posts and having a plurality of openings for exposing upper surfaces of the conductive posts, thereby increasing the package density and protecting the chip and the interconnection structure from being adversely affected by intrusion of moisture.

CROSS-REFERENCES TO RELATED APPLICATIONS

This application claims under 35 U.S.C. § 119(a) the benefit of Taiwanese Application No. 103100019, filed Jan. 2, 2014, the entire contents of which is incorporated herein by reference.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to semiconductor packages and fabrication methods thereof, and more particularly, to a semiconductor package having conductive posts and a fabrication method thereof.

2. Description of Related Art

In recent years, package on package (PoP) structures have become a focus since they meet the miniaturization requirement of electronic products by saving surface area of substrates and at the same time have an improved processing performance.

In a conventional PoP structure, solder balls serve as an interconnection structure for electrically connecting a lower packaging substrate and an upper electronic element. However, to prevent solder bridging during a reflow process, the pitch between the solder balls must be greater than 300 um. As such, the interconnection structure occupies a large area of the packaging substrate and limits the I/O density of the overall package structure.

Further, since the solder ball interconnection structure must be higher than chips on the substrate, the height of the PoP structure as well as the thickness of an electronic device having the PoP structure cannot be effectively reduced.

Furthermore, since no encapsulant is formed between the lower packaging substrate and the upper electronic element, the chips on the packaging substrate and the interconnection structure are susceptible to intrusion of moisture.

Therefore, there is a need to provide a semiconductor package and a fabrication method thereof so as to overcome the above-described drawbacks.

SUMMARY OF THE INVENTION

In view of the above-described drawbacks, the present invention provides a semiconductor package, which comprises: a packaging substrate having opposite first and second surfaces and a plurality of first and second conductive pads formed on the first surface; a chip having opposite active and inactive surfaces and disposed on the first conductive pads via the active surface thereof; a plurality of conductive posts formed on the second conductive pads, respectively; and a first encapsulant formed on the first surface of the packaging substrate for encapsulating the chip and the conductive posts and having a plurality of openings for exposing upper surfaces of the conductive posts.

The present invention further provides a method for fabricating a semiconductor package, which comprises the steps of: providing a packaging substrate having opposite first and second surfaces and a plurality of first and second conductive pads formed on the first surface; forming a plurality of conductive posts on the second conductive pads, respectively; displaying a chip having opposite active and inactive surfaces on the first conductive pads via the active surface thereof; forming a first encapsulant on the first surface of the packaging substrate for encapsulating the chip and the conductive posts; and removing upper portions the first encapsulant and the conductive posts such that upper surfaces of the first encapsulant and the conductive posts are flush with the inactive surface of the chip.

The present invention further provides another method for fabricating a semiconductor package, which comprises the steps of: providing a packaging substrate having opposite first and second surfaces and a plurality of first and second conductive pads formed on the first surface; forming a plurality of conductive posts on the second conductive pads, respectively; disposing on the first conductive pads a chip having opposite active and inactive surfaces via the active surface thereof; forming a first encapsulant on the first surface of the packaging substrate for encapsulating the chip and the conductive posts; and forming a plurality of openings in the first encapsulant for exposing upper surfaces of the conductive posts.

The semiconductor package of the present invention uses the conductive posts instead of the conventional solder balls as an interconnection structure for a PoP structure and the upper surfaces of the encapsulant and the conductive posts are flush with the inactive surface of the chip, thereby increasing the package density, reducing the package thickness and saving the surface area of the packaging substrate. Further, the encapsulant formed between the lower packaging substrate and an upper electronic element protects the chip and the interconnection structure from being adversely affected by intrusion of moisture.

BRIEF DESCRIPTION OF DRAWINGS

FIGS. 1A to 1G are schematic cross-sectional views showing a method for fabricating a semiconductor package according to the present invention;

FIGS. 1F′ and 1G′ are schematic cross-sectional views showing another embodiment of FIGS. 1F and 1G; and

FIGS. 1D″ and 1G″ are schematic cross-sectional views showing a further embodiment of FIGS. 1D and 1G

DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS

The following illustrative embodiments are provided to illustrate the disclosure of the present invention, these and other advantages and effects can be apparent to those in the art after reading this specification.

It should be noted that all the drawings are not intended to limit the present invention. Various modifications and variations can be made without departing from the spirit of the present invention.

FIGS. 1A to 1G are schematic cross-sectional views showing a method for fabricating a semiconductor package according to the present invention.

Referring to FIG. 1A, a packaging substrate 10 is provided. The package substrate 10 has opposite first and second surfaces 10 a, 10 b and a plurality of first and second conductive pads 100, 102 formed on the first surface 10 a. Further, the packaging substrate 10 can have a plurality of third conductive pads 116 formed on the second surface 10 b of the packaging substrate 10 and a plurality of conductive through holes 114 formed between the second conductive pads 102 and the third conductive pads 116 and penetrating the packaging substrate 10 for electrically connecting the second conductive pads 102 and the third conductive pads 116. Furthermore, a solder mask layer 118 can be formed on the second surface 10 b of the packaging substrate 10 and have a plurality of openings 118 a for exposing the third conductive pads 116.

Referring to FIG. 1B, a plurality of conductive posts 104 are formed on the second conductive pads 102, respectively. The conductive posts 104 can be made of, but not limited to, copper.

Referring to FIG. 1C, a chip 20 having opposite active and inactive surfaces 20 a, 20 b is provided and disposed on the first conductive pads 100 via the active surface 20 a thereof. At this point, upper surfaces of the conductive posts 104 may be higher than the inactive surface 20 b of the chip 20. In an embodiment, the active surface 20 a of the chip 20 has a plurality of copper bumps 200 with a solder material 202 thereon. The solder material 202 is reflowed to electrically connect the copper bumps 200 of the chip 20 and the first conductive pads 100 of the packaging substrate 10, thereby flip-chip disposing the chip 20 on the first conductive pads 100. After the chip 20 is disposed on the first conductive pads 100, an underfill 106 can further be formed between the chip 20 and the packaging substrate 10 for encapsulating the first conductive pads 100, the solder material 202 and the copper bumps 200.

Referring to FIG. 1D, a first encapsulant 108 is formed on the first surface 10 a of the packaging substrate 10 for encapsulating the chip 20 and the conductive posts 104.

Referring to FIG. 1E, a portion of the first encapsulant 108 and a portion of the conductive posts 104 are removed such that upper surfaces of the first encapsulant 108 and the conductive posts 104 are flush with the inactive surface 20 b of the chip 20. Also, a portion of the chip 20 can be removed. As such, the overall structure has a predetermined thickness. It should be noted that whether the conductive posts 104 or the chip 20 is partially removed is determined by which one of them is higher than the predetermined thickness. The removing method can be, but not limited to, brushing or grinding. Further, an insulating layer (not shown) can be formed on the first encapsulant 108 and have a plurality of openings for exposing the upper surfaces of the conductive posts 104.

Referring to FIG. 1F, upper portions of the conductive posts 104 are removed such that upper surfaces of the conductive posts 104 are lower than the inactive surface 20 b of the chip 20. The removing method can be, but not limited to, etching. Further, a surface processing layer 110 can be formed on the upper surfaces of the conductive posts 104, and a plurality of solder balls 120 can be formed or mounted on the third conductive pads 116 in the openings 118 a of the solder mask layer 118.

Referring to FIG. 1G an electronic element 30 is disposed on the conductive posts 104 and electrically connected to the conductive posts 104 through a plurality of conductive elements 300 thereof. Then, a second encapsulant 40 is formed on the first encapsulant 108 for encapsulating the electronic element 30.

FIGS. 1F′ and 1G′ show another embodiment of FIGS. 1F and 1G The present embodiment differs from the above-described embodiment in that the upper surfaces of the conductive posts 104 are flush with the inactive surface 20 b of the chip 20.

Referring to FIGS. 1F′ and 1G′, a surface processing layer 110 is formed on the upper surfaces of the conductive posts 104 first and then an insulating layer 112 is formed on the inactive surface 20 b of the chip 20 and the first encapsulant 108 and has a plurality of openings 112 a for exposing the conductive posts 104. In an alternative embodiment, the insulating layer 112 can be formed before the surface processing layer 110 is formed on the upper surfaces of the conductive posts 104. Thereafter, an electronic element 30 is disposed on the conductive posts 104 and a second encapsulant 40 is formed on the insulating layer 112 for encapsulating the electronic element 30, thus forming a semiconductor package of FIG. 1G′.

FIGS. 1D″ and 1G″ are schematic cross-sectional views showing a further embodiment of FIGS. 1D and 1G. In the present embodiment, the upper surfaces of the conductive posts 104 and the first encapsulant 108 are higher than the inactive surface 20 b of the chip 10, and the upper surface of the first encapsulant 108 has a plurality of openings 108 a for exposing the upper surfaces of the conductive posts 104.

Referring to FIG. 1D″, after the first encapsulant 108 is formed as in FIG. 1D, a plurality of openings 108 a are formed in the first encapsulant 108 for exposing the upper surfaces of the conductive posts 104. Thereafter, a surface processing layer 110 is formed on the upper surfaces of the conductive posts 104. Then, an electronic element 30 is disposed on the conductive posts 104 as in FIG. 1G and a second encapsulant 40 is formed on the first encapsulant 108 for encapsulating the electronic element 30, thus forming a semiconductor package of FIG. 1G″. In addition, an insulating layer (not shown) can be formed on the first encapsulant 108 and have a plurality of openings for exposing the upper surfaces of the conductive posts 104. As such, the second encapsulant 40 is formed on the insulating layer.

Referring to FIG. 1G, the semiconductor package of the present invention includes a packaging substrate 10 having opposite first and second surfaces 10 a, 10 b and a plurality of first and second conductive pads 100, 102 formed on the first surface 10 a; a chip 20 having opposite active and inactive surfaces 20 a, 20 b and disposed on the first conductive pads 100 via the active surface 20 a thereof; a plurality of conductive posts 104 formed on the second conductive pads 102, respectively; and a first encapsulant 108 formed on the first surface 10 a of the packaging substrate 10 for encapsulating the chip 20 and the conductive posts 104 and having a plurality of openings 108 a for exposing upper surfaces of the conductive posts 104.

In an embodiment, the first conductive pads 100 and the second conductive pads 102 are embedded in and exposed from the first surface 10 a of the packaging substrate 10.

In an embodiment, the packaging substrate 10 further includes a plurality of third conductive pads 116 formed on the second surface 10 b of the packaging substrate 10, and a plurality of conductive through holes 114 formed between the second conductive pads 102 and the third conductive pads 116 and penetrating the packaging substrate 10 for electrically connecting the second conductive pads 102 and the third conductive pads 116. In an embodiment, the third conductive pads 116 are embedded in and exposed from the second surface 10 b of the packaging substrate 10. Further, a solder mask layer 118 can be formed on the second surface 10 b of the packaging substrate 10 and have a plurality of openings 118 a for exposing the third conductive pads 116. Moreover, a plurality of solder balls 120 can be formed or mounted on the third conductive pads 116 in the openings 118 a of the solder mask layer 118.

In an embodiment, the active surface 20 a of the chip 20 has a plurality of copper bumps 200 with a solder material 202 thereon. The solder material 202 is reflowed to electrically connect the copper bumps 200 of the chip 20 and the first conductive pads 100 of the packaging substrate 10, thereby flip-chip disposing the chip 20 on the first conductive pads 100.

In an embodiment, an underfill 106 is formed between the chip 20 and the packaging substrate 10 for encapsulating the first conductive pads 100, the solder material 202 and the copper bumps 200.

The conductive posts 104 can be made of copper. In the present embodiment of FIG. 1G, the upper surfaces of the conductive posts 104 are lower than the inactive surface 20 b of the chip 20. Further, a surface processing layer 110 can be formed on the upper surfaces of the conductive posts 104.

The semiconductor package can further include an electronic element 30 having a plurality of conductive elements 300 formed or mounted thereon. The electronic element 30 can be a semiconductor chip or a package structure. The electronic element 30 is electrically connected to the conductive posts 104 through the conductive elements 300.

Further, a second encapsulant 40 can be formed on the first encapsulant 108 for encapsulating the electronic element 30.

In addition, an insulating layer can be formed on the first encapsulant 108 and have a plurality of openings for exposing the upper surfaces of the conductive posts 104. As such, the second encapsulant 40 is formed on the insulating layer.

Referring to FIG. 1G′, in the semiconductor package according to another embodiment of the present invention, the upper surfaces of the conductive posts 104 are flush with the inactive surface 20 b of the chip 20. An insulating layer 112 is formed on the chip 20 and the first encapsulant 108 and has a plurality of openings 112 a for exposing the conductive posts 104. Further, a second encapsulant 40 is formed on the insulating layer 112 for encapsulating the electronic element 30. The insulating layer 112 can be, but not limited to, a solder mask layer. In the present embodiment, a surface processing layer 110 is further formed on the upper surfaces of the conductive posts 104.

Referring to FIG. 1G″, in the semiconductor package according to another embodiment of the present invention, the upper surfaces of the conductive posts 104 and the first encapsulant 108 are higher than the inactive surface 20 b of the chip 20. In the present embodiment, a surface processing layer 110 is formed on the upper surfaces of the conductive posts 104, and the surface processing layer 110 is flush with or lower than the upper surface of the first encapsulant 108. Further, an insulating layer can be formed on the first encapsulant 108 and have a plurality of openings for exposing the upper surfaces of the conductive posts 104. As such, the second encapsulant 40 is formed on the insulating layer.

Therefore, by forming an encapsulant between the lower packaging substrate and the upper electronic element, the present invention protects the chip and the interconnection structure from being adversely affected by intrusion of moisture. Further, by removing upper portions of the first encapsulant and the conductive posts as well as a portion of the chip to cause the upper surfaces of the first encapsulant and the conductive posts to be flush with the inactive surface of the chip, the present invention reduces the thickness of the semiconductor package. Furthermore, compared with the conventional solder balls, the conductive posts used as the interconnection structure between the packaging substrate and the electronic element have lower height and smaller pitch, thereby reducing the thickness and increasing the I/O density of the semiconductor package.

The above-described descriptions of the detailed embodiments are only to illustrate the preferred implementation according to the present invention, and it is not to limit the scope of the present invention. Accordingly, all modifications and variations completed by those with ordinary skill in the art should fall within the scope of present invention defined by the appended claims. 

What is claimed is:
 1. A semiconductor package, comprising: a packaging substrate having opposite first and second surfaces and a plurality of first and second conductive pads formed on the first surface; a chip having opposite active and inactive surfaces and disposed on the first conductive pads via the active surface thereof, a plurality of conductive posts formed on the second conductive pads, respectively; a first encapsulant formed on the first surface of the packaging substrate for encapsulating the chip and the conductive posts and having a plurality of openings for exposing upper surfaces of the conductive posts, an insulating layer formed on and directly contacting the chip and the first encapsulant and having a plurality of insulating openings for exposing the conductive posts, wherein the upper surfaces of the conductive posts are coplanar with the inactive surface of the chip and the first encapsulant; and further comprising a plurality of third conductive pads formed on the second surface of the packaging substrate, and a plurality of conductive through holes formed between the second conductive pads and the third conductive pads and penetrating the packaging substrate for electrically connecting the second conductive pads and the third conductive pads.
 2. The package of claim 1, further comprising an electronic element having a plurality of conductive elements and electrically connected to the conductive posts through the conductive elements.
 3. The package of claim 2, wherein the electronic element is a semiconductor chip or a package structure.
 4. The package of claim 2, further comprising a second encapsulant formed on the first encapsulant for encapsulating the electronic element.
 5. The package of claim 1, wherein the conductive posts are made of copper.
 6. The package of claim 1, further comprising a surface processing layer formed on the upper surfaces of the conductive posts.
 7. The package of claim 1, further comprising an underfill formed between the chip and the packaging substrate. 